The AS Configuration Serial Output Timing Diagram defines the timing parameters for the Intel Agilex design. It allows you to create a multi-partition file for your design. This step is the essential part of the configuration. The Intel Quartus Prime Pro Edition tools do not require the location of the decision image. In addition, the SPT contains a pointer to the decision data and one factory image. This configuration file will replace the standard firmware. This SPT contains up to 507 application images and one factory image. The Intel Quartus Prime Programming File Generator will generate an SPT. Afterward, run the Intel Agilex Configuration User Guide and save the changes. Alternatively, you can check the status of the nCONFIG rsu_status command. This software will provide you with the current location of the error and the details.
The first step in configuring an Intel Agilex design is to open the Intel Quartus Prime software and select the relevant settings file.
In addition, Agilex FPGA also supports Optane DC Persistent Memory (OPRAM). The Agilex FPGA can connect to various technologies such as High Bandwidth Memory (HBM) and next-generation 112G transceivers. The Agilex FPGA is based on similar design principles as the Stratix but has several hardened features and external connections that are more versatile and capable of supporting various technologies.
